Video decoder

ABSTRACT

A control device, system and method for multi-pixel reading provides a processor receiving multi-pixel, uses memory units wherein each memory unit sequentially receiving a writing enable signal, and then receiving and storing multi-pixel. Simultaneously, the processor having multi-data bus receives multi-pixel of the each memory unit output. The clock of the enabling all the memory units is less then the delay of the processor reading, so that reducing the spare time of the image decoding system and reducing the reading time of the reading image.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a control device, system andmethod for data reading, and more particularly to a control device,system and method for multi-byte reading.

2. Description of the Prior Art

JPEG, Joint Photographic Experts Groups, is basically a data processingmethod that normally includes a recovering (decoding) method. Referringto FIG. 1, it shows a system, which normally decodes something with adual buffer within a system. The image data is processed by a Huffmandecoder (not shown) and an Inverse quantifier (not shown). Then, theIDCT (Inverse Discrete Cosine Transform) block 110 processes the dataand outputs it to be stored in the first buffer 120. When IDCT block 110fills the first buffer 120 with data, a signal is sent to inform the32-bit processor 150. And the 32-bit processor 150 reads the firstbuffer's data by switching the multiplexer 140. At this time, the IDCTblock 110 continuously processes the image data and outputs the data tobe stored in the second buffer 130.

Generally, it is an I/O (input and output) action that the processorreads the first buffer's data. It means that a delay happens between thetime that the processor is informed and the time of the actual reading.For example: based on the clock unit, the delay is about 6 to 7 systemclocks. However, the delay in the prior art causes the processor toidle. Next, the processor reads the data of the first buffer based on an8-bit unit for JPEG. It only can process 8 bits of data for JPEG eventhe processor with 32 bits can process 32 bits of data. As a result, theprocessor can not work efficiently.

According to the previous mentioned disadvantage of the multi-bitreading, a new and improved device, system and method is needed formulti-bit reading to solve the problems in the prior art such as: how touse the delay when the processor reads the data, how to provide themulti-bit data for reading and how to improve the efficiency of theprocessor.

SUMMARY OF THE INVENTION

According to the defects of the prior art, the well-known multi-bitreading, such as: the processing time is delayed and the system is idle,and the efficiency of the processor is questioned. The object of theinvention invention provides a device, system and method for multi-bitreading, which improves the above-mentioned disadvantage.

The object of the invention provides a device, system and method forprocessor reading. For the processor reading and writing image data intoregisters is in the delay period of the processor reading clock.

The object of the invention also provides a device, system and methodfor improving the efficiency of the processor reading. By storingmulti-byte image data, the processor reads the reading multi-byte dataduring a reading sequence. This is the way to fully utilize the databus.

The object of the invention further provides a device, system and methodfor processing data of the different compressing format. The inventioncan utilize JPEG and MPEG 2 format data.

Accordingly, the said objects of the invention provides a device, systemand method for multi-byte reading. It provides a processor receivingmulti-byte image data. By utilizing a portion of the memory units, afterevery memory unit sequentially receives the writing, the signals areenabled respectively, therefore, receiving and storing the multi-byteimage data. When IDCT (Inverse Discrete Cosine Transform) unit informsthe processor to read data, by the multi-byte bus of the processor, theprocessor simultaneously receives the output of these memory units.Herein, the clock that's enabling all the memory units has less delayfor the processor reading.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic block diagram illustrating a normal decompressingimage data system with a dual buffer according to the prior art;

FIG. 2 is a schematic block diagram illustrating a decompressing imagedata system with a dual buffer according to the invention;

FIGS. 3A and 3B are different schematic block diagrams illustrating onecontrol circuit according to the invention; and

FIG. 4 is a schematic flow chart illustrating decoding system.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Some sample embodiments of the invention will now be described ingreater detail. Nevertheless, it should be recognized that the presentinvention could be practiced in a wide range of procedures.

The present invention will be described in detail with reference to theaccompanying drawings. It should be noted that the drawings are ingreatly simplified form and in order to provide a clear illustration andunderstanding of the present invention.

Referring to FIG. 2, it is an embodiment of decompressing image dataaccording to this invention. The IDCT (Inverse Discrete CosineTransform) unit 210 connects to a plurality of buffers (For example: thefirst buffer 220 and the second buffer 230) for receiving image data,writing data to buffers and transmitting a signal to the processor 250.A plurality of buffers connects to the control circuit 260 through themultiplexer 240. And the control circuit 260 connects to the processor250. In one embodiment, the first buffer 220 and second buffer 230 aregeneral memory devices, for example: Random Access Memory, RAM. Next,the processor 250 is a general processor with the 32-bit bus and theinput/output function. However, it is not limited. The more bits theprocessor has, the more merit the invention has. Between the time ofpreparing to send and receive the data and the time of actuallyreceiving the data, the processor 250 has a clock delay, which isinduced by the physical characters of the hardware device. In oneembodiment, the processor 250 has a 6 to 7 system clocks delay. Theclock delay is not limited here, and the more clock delays with theprocessor 250 the more distinct merits the present invention has.

The control circuit 260 receives data from the first buffer 220 and thesecond buffer 230, and provides image data to the processor 250. Theprocessor 250 does not directly read the data of the buffers that isconnected to the IDCT unit 210. Which means that the first buffer 220 orthe second buffer 230 could transmit the image data through themultiplexer 240 to the control circuit 260 when the processor 250 readsis in the “idle” state. Then, the processor 250 reads the data directlyfrom the control circuit 260, while actually processing the readingdata. There, the processor 250 could read the data with a wide range forimproving the efficiency of the processor. For example: the range of thedata read can be increased from 1 byte to 2 bytes or to 4 bytes. It isnoted that the time of transmitting the image data to the controlcircuit 260 must take less than time then the clock reading of theprocessor 250.

The multiplexer 240 control the Image data that's transmitting from thefirst buffer 220 or the second buffer 230 to the control circuit 260.The multiplexer 240 provides a data path for the data of first buffer220 transmitting to the control circuit 260, when the stored data of thefirst buffer 220 is waiting for the processor 250 to read. At the sametime, the IDCT unit 210 receives the processed image data and storesthem in the second buffer 230. Similarly, when the data of the secondbuffer 230 is waiting for the processor 250 to read, the multiplexer 240provides a data path for the data of the second buffer 230 transmittingto the control circuit 260; At this time, the IDCT unit 210 receives theprocessed image data and stores them in the first buffer 220.

Referring to FIG. 3A, it is an embodiment of the control circuitaccording to this invention. The control circuit 260 includes the inputselection unit and memory units. The input selection unit in oneembodiment, for instance: the multiplexer 240, is used to receive aplurality of the input image data 22 a and 22 b and to output data 23 tomemory unit(s). Herein, the input image data 22 a comes from the firstbuffer, and the input image data 22 b comes from the second buffer. Itis noted that the control circuit of this invention is not limited inthat the multiplexer as the input selection unit. The control circuit issuitable for any designed logic circuit to replace the multiplexer. Thememory units, for example: the registers 2602, 2604, 2606 and 2608,respectively receives the writing enable signals 24 a, 24 b, 24 c and 24d, that are corresponded and controlled by the control signal units 25 ato 25 d respectively. After receiving the corresponded writing enablesignal, each memory unit respectively receives the data 23 from themultiplexer 240 and further outputs the necessary data 26 a, 26 b, 26 c,26 d and 26 e to the corresponding processor, such as processor 250. Itis noted that the writing enable signals 24 a, 24 b, 24 c and 24 d, bycorresponding clock times, sequentially writing enable the register2602, 2604, 2606 and 2608. The control signal units 25 a to 25 d can beinside of the control unit 260 or outside of the control unit 260. Inthe embodiment, the time of the enabling all registers is no more thanthe delay of the processor reading clock. In the embodiment, everywriting enable signal enables a register for a clock and the embodimentfor example is 4 accumulated clocks. The enabling time, 4 clocks, doesnot exceed the processor delay clock, 6 to 7 clocks. In the embodiment,it further includes a data bus of a plurality of byte data (not shown).The data bus is for receiving and transmitting the data of all thememory units (register 2602, 2604, 2606 and 2608).

Next, the invention suits many kinds of compressed image data, such as:Motion Picture Experts Group 2, MPEG 2, and JPEG. Different compressedimage data has different bit numbers (especially for writing enablesignal), for example: MPEG 2 has 9 bits data and JPEG has 8 bits data.Referring to FIG. 3B. The invention can further include a multiplexer2603 for selecting between different bit data and the multiplexer 2603outputs a data 26 e (the multiplexer is not needed as the FIG. 3A, Ifthe input is not different bit data). The register 2602 and the register2604 connected to the multiplexer 2603 have different pin numbers fromeach other. In one embodiment, the register 2602 and the multiplexer 240connected with 9 pins and the register 2604 and the multiplexer 240connected with 8 pins. In addition to, the register 2606, the register2608 and the multiplexer 240 connect with 8 pins, too. Next, theregister 2602 has two different data outputs, one is 8 bits output, data26 a, and the other one is the highest bit or lowest bit of the output.And the register 2604 has the output, one is 7 bits output, data 26 b,and the other one is the first bit of the output to the multiplexer2603. When the decoding system applies in data inputting of MPEG 2, themultiplexer 2603 select the data from the register 2602 and outputs thebit data, 26 e, and 8 bit data, 26 a. The bit data, 26 e, and the 8 bitdata combine a 9 bit data for doing motion compensation. When thedecoding system applies in data inputting of JPEG, the multiplexer 2603selects the data from the register 2604 and outputs a bit data, 26 e,and 7 bit data, 26 b. The bit data, 26 e, and the 7 bit data combine an8 bit data. In other words, the multiplexer 2603 outputs different data26 e by referring to the input format, and then the processor 250controlled by the control circuit 260, can select the data from theregister 2602 or the register 2604. Herein, the other registers are notconnected to the multiplexer 2603, in the embodiment such as: register2606 and 2608, have 8 bits output data, respectively, such as 26 c and26 d.

According to the previous said discussion, the received data of theprocessor is 32 bits and its equal to the bit numbers of the data bus.In the invention, the bit numbers of the output of the plurality ofregister is strongly close to the bit numbers of the data bus, so thatthe processor can read once for receiving the data that is equal to thebit numbers of the data bus. The processor can read multi-byte imagedata, efficiently utilizing the bit numbers of the data bus and havemaximum performance of the data bus. One must explain that 32 bits donot limit the control circuit of the invention. And it is not limited bythe 4-clock system delay. The only limitations are the following: thebit number of the data is no more than the bit number of the data bus ofthe processor, the processor can read the multi-byte data, and the totalclock is not more than the reading delay of the processor. Any variationlimited by the above limitations is included in the scope of theinvention.

FIG. 4 shows a flow chart of an embodiment of the decoding system in theinvention. After that the typical image data goes through the Huffmandecoder and the Inverse quantizer, the typical data are inputted to theIDCT unit. The data goes through the IDCT unit and is written in abuffer and then at least one buffer full of data (step 410). When thebuffer is full, the IDCT unit informs the processor to read the data(step 420). The processor has a “m” bit data bus and a delay “n” that isthe time between the reading signal received and that of the executionstarted. At the time of sending the read signal, the data of the bufferwrite in registers in sequence (step 430). The total time of the datawriting in a plurality of registers is less than the time of the delay“n”. The processor reads the data of the registers at the same time(440). Wherein the processor reads the data and has a bit number whichis substantially equal (or not less than) to “m”.

Because the control circuit of this invention applies to a decodingsystem with the dual buffer, the idle of reading image data and thewriting in buffer of the IDCT unit do not depend on the acting of theprocessor. Next, the control circuit includes some registers. Theregister can receive data when clocks delay in the processor. Thisreduces the idle time. The total output bit of the register is close tothe data bus, so as the processor can have the maximum performance ofthe data bus.

Other embodiments of the invention will appear to those skilled in theart from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples to be considered as exemplary only, with a true scope andspirit of the invention being indicated by the following claims.

1. A controlling device for outputting multi-byte image data,comprising: a plurality of memory units, each said memory unit receivingand storing a plurality of bit image data, wherein said plurality ofmemory units simultaneously and correspondingly output said plurality ofbit image data, and the sum of said plurality of said bit image dataequal to a plurality of byte image data; and a plurality of controlsignal units for generating a plurality of writing enable signals, saidplurality of writing enable signals being corresponding to saidplurality of memory units, respectively, wherein said plurality ofwriting enable signals control said plurality of memory units to bestored in said plurality of bit image data in sequence.
 2. Thecontrolling device according to claim 1, wherein a plurality of saidmemory units are a plurality of registers.
 3. The controlling deviceaccording to claim 1, wherein the controlling device further comprisesat least one multiplexer being connected with at least two said memoryunits.
 4. The controlling device according to claim 3, wherein saidplurality of bit image data from any said memory units connected to saidmultiplexer is chosen from the groups selected as follows: a first bitdata and a second bit data, wherein said first bit data is not equal tosaid second bit data.
 5. The controlling device according to claim 4,wherein said first bit data is not more than 1 bit data.
 6. Thecontrolling device according to claim 4, wherein the bit number of saidbit image data received and stored in any said memory units connected tosaid multiplexer is not equal to the bit number of said bit image datareceived and stored in the others said memory units connected to saidmultiplexer.
 7. The controlling device according to claim 4, whereinsome said memory units connected to said multiplexer output said bitimage data is integrated to build said plurality of byte image data. 8.The controlling device according to claim 4, wherein said multiplexeroutputs one of said first bit data of one said memory unit connected tosaid multiplexer.
 9. The controlling device according to claim 1,further comprising a data bus having a plurality of byte fortransmitting a plurality of said byte image data.
 10. A controllingsystem for outputting multi-byte image data, comprises: an inversediscrete consine transform (IDCT) unit for processing a plurality ofimage data; a plurality of buffers for receiving said plurality of imagedata processed by said inverse discrete consine transform (IDCT) unit; amultiplexer connected to said plurality of buffers; a control circuitconnected to said multiplexer for utilizing said multiplexer to movesaid image data from said buffers to said control circuit; and aprocessor, connected to said control circuit, for receiving said imagedata from said control circuit simultaneously.
 11. The controllingsystem according to claim 10, further comprising a data bus fortransmitting data from said control circuit to said processor, whereinthe bit number of said data bus is not less than the total bit number ofsaid buffers.
 12. The controlling system according to claim 10, whensaid processor being idle, said buffers transmit said plurality of imagedata through said multiplexer to said control circuit, and when saidprocessor reading, said processor reads a plurality of said image datafrom said control circuit directly.
 13. The controlling system accordingto claim 10, wherein said multiplexer controls said image datatransmitted between said buffers and said control circuit, and at thesame time, only one said buffer transmits data to said control circuitand other said buffers receive said image data processed by said inversediscrete consine transform (IDCT) unit.
 14. The controlling systemaccording to claim 10, when any said buffer is full of data, saidcontrol circuit moves data of said filled buffer to said control circuitfor enabling said buffer to receive data from said inverse discreteconsine transform (IDCT) unit.
 15. The controlling system according toclaim 10, when said control circuit is full of data, said IDCT unitsends a signal to said processor for informing said processor to readsaid control circuit.
 16. A method for outputting multi-byte image data,comprising: receiving a plurality of writing enable signals in sequence,when receiving any one of said writing enable signal, receiving andstoring at least one bit image data to at least one memory unit; andoutputting a plurality of said bit image data simultaneously.
 17. Themethod according to claim 16, wherein said outputting simultaneouslystep uses a data bus of a plurality of byte outputting and uses aprocessor for reading a plurality of said bit image data.
 18. The methodaccording to claim 17, wherein said processor having delay, said delayis more than the duration of spending said receiving said writing enablesignals step
 19. The method according to claim 16, further comprising aplurality of buffers for receiving said bit image data, and when anysaid buffer full of data, sends writing enable signal in sequence formoving said bit image data from said buffers to a plurality of memoryunit.